As electronic circuit packaging performance increases, the demand for higher wiring and component density also increases. To meet the higher density requirements, surface mount technology (SMT), such as flip chip attach (FCA), direct chip attach (DCA), ball grid array(BGA), and similar technology is required. In most cases, the copper interconnecting pads have to be contamination and oxidation free to achieve adequate wetability.
In order to achieve adequate wetting and prevent corrosion of the copper pads during application of conductive epoxy, it is necessary to deposit a thin gold overlay onto the copper base. Typically, a thin nickel interlayer is required between the copper and gold overlay to assure adequate bonding of the gold overlay to the underlying copper surface.
However, when the circuit features on the substrates are fabricated by the full additive process, conventional electroless gold deposition causes bridging between the lines and/or pads defining the electrical circuit features on the substrate, that may be spaced apart on the order of about 2 mil or less. The fully additive process used to define the copper features relies on having a palladium catalyst on the surface to be plated. This is provided by seeding the surface with a suitable palladium seeder such as palladium chloride. Heretofore, if the primary catalyst is not removed prior to gold conformal plating, gold will plate on the substrate and form shorts bridging between the conductive copper features. It is very difficult to remove the plating seed layer from between closely spaced electrically conductive features.
The present invention is directed to overcoming the problems set forth above. It is desirable to have an effective gold deposition process by which gold may be directly deposited on the exposed surface of previously defined closely spaced copper electronic circuit features, without the need for a nickel surface, and which avoids bridging of gold between conductive circuit features. It is also desirable to have an economical process for forming a thin gold coating on previously defined closely spaced copper circuit features formed by the fully additive process, which does not require removal of the palladium seeder prior to deposition of the gold coating.